The present invention relates to a differential amplifier and a source driver and, particularly, to a differential amplifier incorporated into a source driver that drives a liquid crystal display device and a source driver incorporating the same.
A source driver that drives a liquid crystal display device incorporates a differential amplifier as a source amplifier. The source driver first divides a γ(gamma) voltage applied externally by resistors to generate liquid crystal gray scale reference voltages and then selects a reference voltage by a D/A converter. The selected reference voltage is input to the source amplifier in a voltage follower configuration in order to reduce impedance and make fine adjustments of the reference voltage. An output of the source amplifier is connected to a source terminal of a liquid crystal panel, and a panel pixel capacitor is driven with the output from the source amplifier.
Recent liquid crystal display devices for use as TV or PC displays have a larger screen and higher definition. With such trends, the source driver is required to have a capability to drive a larger load at a higher speed and with a lower power. Particularly, an increase in gray-scale intensity is in progress for higher-definition color liquid crystals, and transition has been made from 260000 colors (6 bits per Red, Green and Blue) to 16.7 million colors (8 bits), and to 1 billion colors (10 bits).
With an increase in the number of bits, a gray-scale voltage input to the source driver increases like 64 gray scales with 6 bits, 256 gray scales with 8 bits, and 1024 gray scales with 10 bits. The increase in gray-scale voltage leads to a decrease in steps of the voltage input to the source driver. Therefore, improvement in output voltage accuracy is required in the source amplifier, and property specifications such as input-output offset, output deviation and amplitude difference deviation are becoming stricter.
FIG. 4 shows a typical circuit which is used as a source amplifier. A differential amplifier 200 shown in FIG. 4 is a so-called Rail-to-Rail amplifier. The differential amplifier 200 is broadly divided into an input stage 210, an intermediate stage 220, and a final stage 230.
FIG. 5 shows a simplified illustration of the differential amplifier 200 shown in FIG. 4. As shown in FIG. 5, a differential amplifier 300 is broadly divided into an input stage 110, an intermediate stage 120, and a final stage 130. The input stage 110 includes differential pairs of reverse conductivity types to each other in order to implement the Rail-to-Rail configuration. Specifically, the input stage 110 includes an Nch differential pair 111 composed of Nch MOS transistors (NchTr) MN11 and MN12 having sources connected in common to a constant current source I11, and a Pch differential pair 115 composed of Pch MOS transistors (PchTr) MP11 and MP12 having sources connected in common to a constant current source I15.
An input voltage range of the differential amplifier 300 is described hereinafter. It is assumed that the “+” power supply (higher power supply) of the source amplifier is VDD, and the “−” power supply (lower power supply) of the source amplifier is VSS. When an input voltage Vin31 input from an input terminal IN31 is as low as near the − power supply voltage VSS, the Pch MOS transistors MP11 and MP12 of the Pch differential pair 115 operate. When, on the other hand, the input voltage Vin31 is as high as near the + power supply voltage VDD, the Nch MOS transistors MN11 and MN12 of the Nch differential pair 111 operate. When the input voltage Vin31 is an intermediate voltage between those, both of the Pch MOS transistors MP11 and MP12 of the Pch differential pair 115 and the Nch MOS transistors MN11 and MN12 of the Nch differential pair 111 operate. Therefore, the source amplifier which uses the differential amplifier 300 can obtain the input stage 110 that operates in the input range of substantially all power supply voltages.
A voltage obtained by resistor-division of a gamma voltage is input to the source amplifier, and the voltage corresponding to a polarity signal POL having 64 gray scales (6 bits) to 256 gray scales (8 bits) for both positive and negative has become mainstream. As the number of bits increases, a difference in luminance between gray scales becomes less recognizable, thus rendering smooth high-quality pictures. However, as the number of bits increases, the D/A converter circuit that selects a voltage generated by the resistor division increases in size.
To avoid this, products with a large number of bits adopts an interpolation function to the source amplifier. FIG. 6 shows a differential amplifier used for the source amplifier having the interpolation function. Referring to FIG. 6, a differential amplifier 400 has a configuration in which an Nch differential pair 112 composed of Nch MOS transistors MN13 and MN14 having sources connected in common to a constant current source I12, and a Pch differential pair 116 composed of Pch MOS transistors MP13 and MP14 having sources connected in common to a constant current source I14 are added to the differential amplifier 300 shown in FIG. 5.
The Nch MOS transistors MN13 and MN14 of the Nch differential pair 112 are connected in parallel with the Nch MOS transistors MN11 and MN12 of the Nch differential pair 111 with their drains connected in common. Likewise, the Pch MOS transistors MP13 and MP14 of the Pch differential pair 116 are connected in parallel with the Pch MOS transistors MP11 and MP12 of the Pch differential pair 115 with their drains connected in common. Further, an input terminal IN2 as an input to the Nch MOS transistor MN14 and the Pch MOS transistor MP14 is also added. Note that an input of the Nch MOS transistor MN12 and the Pch MOS transistor MP12 is the input terminal IN1.
The differential amplifier 400 has an interpolation function that interpolates a voltage which internally divides an input voltage Vin1 input to the input terminal IN1 and an input voltage Vin2 input to the input terminal IN2 with a ratio of 1:1. With the interpolation function, an output voltage Vout of (Vin1+Vin2)/2 can be output.
For example, when an output set voltage is V1, a voltage of V1+α(V) is input to the input terminal IN1, and a voltage of V1−α(V) is input to the input terminal IN2. Then, an intermediate voltage between the input terminals IN1 and IN2, which is V1, is output to the output terminal OUT. Further, when the output set voltage is V1+α(V), a voltage of V1+α(V) is input to both of the input terminals IN1 and IN2. Then, an intermediate voltage between the input terminals IN1 and IN2, which is V1+α(V), is output to the output terminal OUT. On the other hand, when the output set voltage is V1−α(V), a voltage of V1−α(V) is input to both of the input terminals IN1 and IN2. Then, an intermediate voltage between the input terminals IN1 and IN2, which is V1−α(V), is output to the output terminal OUT.
In this manner, in the differential amplifier 400, if there are two levels of input voltages, V1+α(V) and V1−α(V), three levels of output voltages Vout, V1+α(V), V1(V) and V1−α(V), can be output with use of the interpolation function. Specifically, the number of input gray-scale power supply lines can be reduced relative to the number of output gray scales. This eliminates the need to input V1(V) to the differential amplifier 400, which enables reduction of the circuit size of the D/A converter.
However, the differential amplifier 400 has a drawback that, when the output set voltage (i.e. the input voltage) is a voltage near the − power supply voltage VSS or the + power supply voltage VDD, an offset between input and output is deteriorated. This is described hereinafter with reference to FIG. 7. In FIG. 7, the upper part shows an input-output offset voltage Vos of the differential amplifier 400, and the lower part shows the respective states of the Nch differential pairs 111 and 112 and the Pch differential pairs 115 and 116. The horizontal axis indicates the output set voltage. Note that the input voltages have the relationship of Vin1>Vin2, and the input-output offset voltage Vos is Vout−(Vin1+Vin2)/2.
An input voltage that allows the Nch input stage to operate is equal to or higher than VT(MN11˜14)+VDS(I11,I12), which is an operation threshold of the Nch differential pairs 111 and 112. On the other hand, an input voltage that allows the Pch input stage to operate is equal to or higher than VT(MP11˜14)+VDS(I15,I16), which is an operation threshold of the Pch differential pairs 115 and 116. Note that, in this specification, the operation threshold of the Pch differential pairs 115 and 116 is described from the aspect of being a voltage difference from the + power supply voltage VDD, not the absolute value of an input voltage. Specifically, in the Pch differential pairs 115 and 116, “equal to or higher than the operation threshold” means that a potential difference between an input voltage and the + power supply voltage VDD is large, and “equal to or lower than the operation threshold” means that a potential difference between an input voltage and the + power supply voltage VDD is small.
Therefore, referring to FIG. 7, both of the Nch input stage and the Pch input stage operate in the voltage range (4) which is equal to or higher than the operation threshold of the Nch differential pairs 111 and 112 and equal to or higher than the operation threshold of the Pch differential pairs 115 and 116.
On the other hand, in the voltage range (3) which is equal to or lower than the operation threshold of the Nch differential pair 112, the Nch differential pair 112 operates with the threshold or lower, and the Nch differential pair 111 and the Pch input stage operate. Further, in the voltage range (2) which is equal to or lower than the operation threshold of the Nch differential pair 111, only the Nch differential pair 112 is completely off, the Nch differential pair 111 operates with the threshold or lower, and the Pch input stage operates. In the voltage range (1) where the Nch input stage is completely off, only the Pch input stage operates.
Likewise, in the voltage range (5) which is equal to or lower than the operation threshold of the Pch differential pair 115, the Pch differential pair 115 operates with the threshold or lower, and the Pch differential pair 116 and the Nch input stage operate. Further, in the voltage range (6) which is equal to or lower than the operation threshold of the Pch differential pair 116, only the Pch differential pair 115 is completely off, the Pch differential pair 116 operates with the threshold or lower, and the Nch input stage operates. In the voltage range (7) where the Pch input stage is completely off, only the Nch input stage operates.
As is obvious from FIG. 7, in the differential amplifier 400, an input-output offset is deteriorated in the voltage ranges (2), (3), (5) and (7). In this manner, in the differential amplifier 400, use of the interpolation function in the state where a voltage of lower than the operation threshold of the differential pair constituting the input stage 110 is input to one of the input terminals IN1 and IN2 causes degradation of an input-output offset. This means that highly accurate interpolation cannot be performed in the gray-scale which corresponds to the voltage range were an input-output offset is degraded.
The mechanism which causes degradation of an input-output offset in the differential amplifier 400 is described hereinafter, using a case where the output set voltage is V1, and the output set voltage V1 is near the − power supply voltage VSS as an example.
V1+α(V) is input as the input voltage Vin1 to the input terminal IN1, and V1−α(V) is input as the input voltage Vin2 to the input terminal IN2. In this case, it is ideal that an intermediate voltage between the input terminals IN1 and IN2, which is V1, is output as an output voltage Vout to the output terminal OUT.
Assume that the operation threshold of the Nch input stage is V1. The MN11 and MN12 of the Nch differential pair 111 operate because the input voltage Vin, to the input terminal IN1 is equal to or higher than the operation threshold. However, the MN13 and MN14 of the Nch differential pair 112 are in the operating state with the operation threshold or lower because the input voltage Vin2 to the input terminal IN2 is lower than the operation threshold.
In other words, although the Pch input stage performs a negative feedback operation so as to converge on V1 as ideal, the Nch input stage performs a negative feedback operation so that an output converges on V1+α(V) because only the Nch differential pair 111 is operating. Consequently, a difference in convergence voltage arises between the Pch input stage and the Nch input stage, and the output voltage Vout has an offset in the “+” direction, which is the same as +α(V) as a result.
As described above, when outputting a voltage near the − power supply voltage, two Nch differential pairs 111 and 112 stop operating one by one as the input voltages Vin1 and Vin2 get lower, and, in its process, a case arises where one operates in the non-saturation region and the other operates in the saturation region. Likewise, when outputting a voltage near the + power supply voltage, two Pch differential pairs 115 and 116 stop operating one by one as the input voltages V1n1 and Vin2 get higher, and, in its process, a case arises where one operates in the non-saturation region and the other operates in the saturation region. Then, when one operates in the non-saturation region and the other operates in the saturation region, a difference in convergence voltage arises between the Pch input stage and the Nch input stage, which causes degradation in input-output offset.
A technique to address such an issue is disclosed in Japanese Unexamined Patent Application Publication No. 2006-50296. FIG. 8 is a circuit diagram showing a configuration of a differential amplifier 500 disclosed in Japanese Unexamined Patent Application Publication No. 2006-50296. Referring to FIG. 8, the differential amplifier 500 has a configuration in which a determination unit 510 that compares levels of the output voltage Vout and a discrimination signal, and an input stage control unit 520 that controls the input stage 110 are added to the differential amplifier 400 shown in FIG. 6. When the differential amplifier 500 outputs a voltage near the − power supply voltage VSS or the +power supply voltage VDD, it turns off the Nch input stage or the Pch input stage depending on the output voltage Vout and the discrimination signal before degradation in offset occurs.
FIG. 9 is a graph showing an operation waveform of the differential amplifier 500. The upper part of FIG. 9 shows an input-output offset voltage Vos of the differential amplifier 500, and the lower part shows the respective states of the Nch differential pairs 111 and 112 and the Pch differential pairs 115 and 116. The horizontal axis indicates the output set voltage. Note that the input voltages have the relationship of Vin>Vin2, and the input-output offset voltage Vos is Vout−(Vin1+Vin2)/2.
As shown in FIG. 9, when the input voltage is a voltage near the − power supply voltage VSS, the Nch input stage is turned completely off by the input stage control unit 520, and only the Pch input stage operates (voltage range (1)). Therefore, an offset of the Pch input stage appears in the output voltage \Vout from the output terminal OUT. Further, when the input voltage is an intermediate voltage, the Nch input stage and the Pch input stage are both on (voltage range (4)). Therefore, offsets of the Nch input stage and the Pch input stage appear in the output voltage \Vout. On the other hand, when the input voltage is a voltage near the + power supply voltage VDD, the Pch input stage is turned completely off by the input stage control unit 520, and only the Nch input stage operates (voltage range (7)). Therefore, an offset of the Nch input stage appears in the output voltage Vout.